https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107786
--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Philipp Tomsich <ptoms...@gcc.gnu.org>: https://gcc.gnu.org/g:4c7d336b673df2f3bf23bc5e7a69c445a2320c04 commit r13-4201-g4c7d336b673df2f3bf23bc5e7a69c445a2320c04 Author: Philipp Tomsich <philipp.toms...@vrull.eu> Date: Mon Nov 21 12:44:23 2022 +0100 RISC-V: Fix ICE in branch<ANYI:mode>_shiftedarith_equals_zero With the recent improvements to the splitting of special cases of branch patterns on RISC-V, a dependency on an unmerged/in-discussion change for branch-equals-zero slipped in: this allowed a non-X mode to be presented to branch-equals-zero (where only X mode is permissible). This addresses the issue by wrapping the ANYI operand in a paradoxical SUBREG:X (the high bits can be safely ignored, as we we perform an and-immediate before the branch in the pattern). Tested against the GCC testsuite and committed as obvious. gcc/ChangeLog: PR target/107786 * config/riscv/riscv.md (*branch<ANYI:mode>_shiftedarith_equals_zero): Wrap ANYI in a subreg, as our branch instructions only supports X. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr107786-2.c: New test. * gcc.target/riscv/pr107786.c: New test.
