https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105661
--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(In reply to Andrew Pinski from comment #1)
> Basically we don't optimize anything related to volatile memory even into
> the address part. This is basically PR 50677 really.
I should say internally for RTL level we do atomic loads as volatile memory.
(insn 5 4 0 (set (reg:QI 83 [ _5 ])
(mem/v:QI (symbol_ref:DI ("atomic") [flags 0x2] <var_decl
0x7fefa628cab0 atomic>) [-1 S1 A8]))
"/opt/compiler-explorer/gcc-trunk-20221026/include/c++/13.0.0/bits/atomic_base.h":505:24
-1
(nil))
