https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107090
Bug ID: 107090
Summary: [aarch64] sequence logic should be combined with mul
and umulh
Product: gcc
Version: 13.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: zhongyunde at huawei dot com
Target Milestone: ---
* test case: https://godbolt.org/z/x5jMhqW8s
```
# define BN_BITS4 32
# define BN_MASK2 (0xffffffffffffffffL)
# define BN_MASK2l (0xffffffffL)
# define BN_MASK2h (0xffffffff00000000L)
# define BN_MASK2h1 (0xffffffff80000000L)
# define LBITS(a) ((a)&BN_MASK2l)
# define HBITS(a) (((a)>>BN_BITS4)&BN_MASK2l)
# define L2HBITS(a) (((a)<<BN_BITS4)&BN_MASK2)
void mul64(unsigned long in0, unsigned long in1,
unsigned long &l, unsigned long &h) {
unsigned long m, m1, lt, ht, bl, bh;
lt = LBITS(in0);
ht = HBITS(in0);
bl = LBITS(in1);
bh = HBITS(in1);
m = bh * lt;
lt = bl * lt;
m1 = bl * ht;
ht = bh * ht;
m = (m + m1) & BN_MASK2;
if (m < m1) ht += L2HBITS((unsigned long)1);
ht += HBITS(m);
m1 = L2HBITS(m);
lt = (lt + m1) & BN_MASK2; if (lt < m1) ht++;
l = lt;
h = ht;
}
```
* The above source is equel to an mull operater for two 64bits integer vaules,
so it should be fold to similar assemble
```
mul x8,x1,x0
umulh x9,x0,x1
str x8,[x2]
str x9,[x3]
ret
```
