https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106462
--- Comment #1 from Yang Yujie <yangyujie at loongson dot cn> ---
The relevant insn template is:
(define_insn "floatsisf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(float:SF (match_operand:SI 1 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
"cvt.s.w\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
(set_attr "cnv_mode" "I2S")])
It seems that
(match_operand:SI 1 "register_operand "f")
actually matched (during pass_expand):
(subreg/s/u:SI (reg/v:DI 209 [orig:197 c ] [197]))
and curr_insn_transform decided to spill the (reg/v:DI 209) pseudo-register
into FP_REGS, which fails because FP registers are only 32-bit-wide.
My question is: should the reload pass handle this by first assigning (reg:DI)
into a (64-bit) general-purpose hard register, and then emit a move instruction
to fill the floating-point-register operand?
