[Bug target/106038] x86_64 vectorization of ALU ops using xmm registers prematurely

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106038

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuho...@gcc.gnu.org>:

https://gcc.gnu.org/g:605b64251c78f29da32ed807413971339f27d13b

commit r13-1790-g605b64251c78f29da32ed807413971339f27d13b
Author: liuhongt <hongtao....@intel.com>
Date:   Thu Jul 7 14:33:32 2022 +0800

    Extend 16/32-bit vector bit_op patterns with (m,0,i) alternative.

    And split it after reload.

    gcc/ChangeLog:

            PR target/106038
            * config/i386/mmx.md (<code><mode>3): New define_expand, it's
            original "<code><mode>3".
            (*<code><mode>3): New define_insn, it's original
            "<code><mode>3" be extended to handle memory and immediate
            operand with ix86_binary_operator_ok. Also adjust define_split
            after it.
            (mmxinsnmode): New mode attribute.
            (*mov<mode>_imm): Refactor with mmxinsnmode.
            * config/i386/predicates.md
            (register_or_x86_64_const_vector_operand): New predicate.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr106038-1.c: New test.