https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105953
Uroš Bizjak <ubizjak at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Last reconfirmed| |2022-06-14
Status|UNCONFIRMED |NEW
Ever confirmed|0 |1
Target Milestone|--- |12.3
CC| |liuhongt at gcc dot gnu.org
--- Comment #1 from Uroš Bizjak <ubizjak at gmail dot com> ---
Instruction does not accept memory operand for operand 3:
(define_insn_and_split
"*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_ltint"
[(set (match_operand:<ssebytemode> 0 "register_operand" "=Yr,*x,x")
(unspec:<ssebytemode>
[(match_operand:<ssebytemode> 1 "register_operand" "0,0,x")
(match_operand:<ssebytemode> 2 "vector_operand" "YrBm,*xBm,xm")
(subreg:<ssebytemode>
(lt:VI48_AVX
(match_operand:VI48_AVX 3 "register_operand" "Yz,Yz,x")
(match_operand:VI48_AVX 4 "const0_operand")) 0)]
UNSPEC_BLENDV))]
The problematic insn is:
(define_insn_and_split "*avx_cmp<mode>3_ltint_not"
[(set (match_operand:VI48_AVX 0 "register_operand")
(vec_merge:VI48_AVX
(match_operand:VI48_AVX 1 "vector_operand")
(match_operand:VI48_AVX 2 "vector_operand")
(unspec:<avx512fmaskmode>
[(subreg:VI48_AVX
(not:<ssebytemode>
(match_operand:<ssebytemode> 3 "vector_operand")) 0)
(match_operand:VI48_AVX 4 "const0_operand")
(match_operand:SI 5 "const_0_to_7_operand")]
UNSPEC_PCMP)))]
which gets split to the above pattern.
In the preparation statements we have:
if (!MEM_P (operands[3]))
operands[3] = force_reg (<ssebytemode>mode, operands[3]);
operands[3] = lowpart_subreg (<MODE>mode, operands[3], <ssebytemode>mode);
Which won't fly when operand 3 is memory operand...
CC author, g:8fa7216ae0d8
