https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105911
--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jakub Jelinek <ja...@gcc.gnu.org>: https://gcc.gnu.org/g:13ea4a6e830da1f245136601e636dec62e74d1a7 commit r13-1061-g13ea4a6e830da1f245136601e636dec62e74d1a7 Author: Jakub Jelinek <ja...@redhat.com> Date: Mon Jun 13 10:53:33 2022 +0200 i386: Fix up *<dwi>3_doubleword_mask [PR105911] Another regression caused by my recent patch. This time because define_insn_and_split only requires that the constant mask is const_int_operand. When it was only SImode, that wasn't a problem, HImode neither, but for DImode if we need to and the shift count we might run into a problem that it isn't a representable signed 32-bit immediate. But, we don't really care about the upper bits of the mask, so we can just mask the CONST_INT with the mode mask. 2022-06-13 Jakub Jelinek <ja...@redhat.com> PR target/105911 * config/i386/i386.md (*ashl<dwi>3_doubleword_mask, *<insn><dwi>3_doubleword_mask): Use operands[3] masked with (<MODE_SIZE> * BITS_PER_UNIT) - 1 as AND operand instead of operands[3] unmodified. * gcc.dg/pr105911.c: New test.
