https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105773
Richard Earnshaw <rearnsha at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Last reconfirmed| |2022-06-08 Status|UNCONFIRMED |NEW Ever confirmed|0 |1 --- Comment #1 from Richard Earnshaw <rearnsha at gcc dot gnu.org> --- Confirmed. The tricky thing here is the inequality following the logical AND operation. The GT comparison is defined as (Z=0 && N==V), and the logical AND will clear V and set Z & N appropriately. It's important to note that this optimization is not valid in AArch32, because the V flag is not modified by the TST instruction, leaving the flag bit essentially undefined.