https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105825
--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Jakub Jelinek <ja...@gcc.gnu.org>: https://gcc.gnu.org/g:53718316afa45eb0d1c236fbbf2fc0959b08510f commit r13-989-g53718316afa45eb0d1c236fbbf2fc0959b08510f Author: Jakub Jelinek <ja...@redhat.com> Date: Sat Jun 4 10:36:24 2022 +0200 i386: Fix up *_doubleword_mask [PR105825] My PR105778 patch apparently broke the following testcase. If the mask has the top relevant bit clear (i.e. we know we are shifting by 0 to wordsize bits - 1) but doesn't have all the bits below it set, we emit andsi3 before the shift sequence. When the pattern had :SI for that operand, that was just fine, but now that it can be also HImode or for -m64 DImode, we either can use a lowpart or paradoxical subreg to SImode as the following patch, or we use a HImode or DImode AND. This patch does the latter. 2022-06-04 Jakub Jelinek <ja...@redhat.com> PR target/105825 * config/i386/i386.md (*ashl<dwi>3_doubleword_mask, *<insn><dwi>3_doubleword_mask): If top bit of mask is clear, but lower bits of mask aren't all set, use operands[2] mode for the AND operation instead of always SImode. * gcc.dg/pr105825.c: New test.
