https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105744
--- Comment #2 from Kewen Lin <linkw at gcc dot gnu.org> --- This exposes one bug in glibc strncpy power9 implementation In https://sourceware.org/git/?p=glibc.git;a=blob_plain;f=sysdeps/powerpc/powerpc64/le/power9/strncpy.S lbz r0,0(r4) stb r0,0(r3) addi r11,r3,1 addi r5,r5,-1 vspltisb v18,0 /* Zeroes in v18 */ ... L(zero_padding_end): sldi r10,r5,56 /* stxvl wants size in top 8 bits */ stxvl v18,r11,r10 /* Partial store */ blr The code at label "zero_padding_end" is supposed to use v18, but the stxvl will take the 18 as vsx No. instead of vr No, so it ends up to use the wrong register vs18 instead of v18 for the store. The reason why the optimization option matters is that some optimization happen to generate some sequence to modify the value of vs18 then it's not expected to be zero any more.
