https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105731

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Combine:

Trying 41 -> 44:
   41: r120:SI=r119:SI<<0x1a
      REG_DEAD r119:SI
   44: pc={(r120:SI<0)?L114:pc}
      REG_BR_PROB 283038348
Failed to match this instruction:
(parallel [
        (set (pc)
            (if_then_else (ne (zero_extract:SI (reg:SI 119 [ _7 ])
                        (const_int 1 [0x1])
                        (const_int 5 [0x5]))
                    (const_int 0 [0]))
                (label_ref 114)
                (pc)))
        (set (reg/v:SI 120 [ bits ])
            (ashift:SI (reg:SI 119 [ _7 ])
                (const_int 26 [0x1a])))
    ])
Failed to match this instruction:
(parallel [
        (set (pc)
            (if_then_else (ne (zero_extract:SI (reg:SI 119 [ _7 ])
                        (const_int 1 [0x1])
                        (const_int 5 [0x5]))
                    (const_int 0 [0]))
                (label_ref 114)
                (pc)))
        (set (reg/v:SI 120 [ bits ])
            (ashift:SI (reg:SI 119 [ _7 ])
                (const_int 26 [0x1a])))
    ])
Failed to match this instruction:
(parallel [
        (set (pc)
            (if_then_else (ne (and:SI (lshiftrt:SI (reg:SI 119 [ _7 ])
                            (const_int 5 [0x5]))
                        (const_int 1 [0x1]))
                    (const_int 0 [0]))
                (label_ref 114)
                (pc)))
        (set (reg/v:SI 120 [ bits ])
            (ashift:SI (reg:SI 119 [ _7 ])
                (const_int 26 [0x1a])))
    ])
Failed to match this instruction:
(parallel [
        (set (pc)
            (if_then_else (ne (and:SI (lshiftrt:SI (reg:SI 119 [ _7 ])
                            (const_int 5 [0x5]))
                        (const_int 1 [0x1]))
                    (const_int 0 [0]))
                (label_ref 114)
                (pc)))
        (set (reg/v:SI 120 [ bits ])
            (ashift:SI (reg:SI 119 [ _7 ])
                (const_int 26 [0x1a])))
    ])
Successfully matched this instruction:
(set (reg/v:SI 120 [ bits ])
    (ashift:SI (reg:SI 119 [ _7 ])
        (const_int 26 [0x1a])))
Successfully matched this instruction:
(set (pc)
    (if_then_else (ne (zero_extract:SI (reg:SI 119 [ _7 ])
                (const_int 1 [0x1])
                (const_int 5 [0x5]))
            (const_int 0 [0]))
        (label_ref 114)
        (pc)))
allowing combination of insns 41 and 44
original costs 4 + 14 = 18
replacement costs 4 + 14 = 18
modifying insn i2    41: r120:SI=r119:SI<<0x1a
deferring rescan insn with uid = 41.
modifying insn i3    44:
{pc={(zero_extract(r119:SI,0x1,0x5)!=0)?L114:pc};clobber scratch;}
      REG_DEAD r119:SI
      REG_BR_PROB 283038348
deferring rescan insn with uid = 44.

The cost for the following instruction is wrong:
(jump_insn 113 110 114 13 (parallel [
            (set (pc)
                (if_then_else (eq (zero_extract:SI (reg:SI 119 [ _7 ])
                            (const_int 1 [0x1])
                            (const_int 5 [0x5]))
                        (const_int 0 [0]))
                    (label_ref 59)
                    (pc)))
            (clobber (scratch:SI))
        ]) "/app/example.cpp":33:26 961 {*tbit_cbranch}
     (expr_list:REG_DEAD (reg:SI 119 [ _7 ])
        (int_list:REG_BR_PROB 457091900 (nil)))
 -> 59)

It should be 18 since it gets splitted into two one which has a cost of 4 and
another which is a cost of 14.

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