https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103897
--- Comment #3 from Hongtao.liu <crazylht at gmail dot com> ---
For 1), we have
(define_insn "*sse4_1_<code>v4hiv4si2<mask_name>_1"
[(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v")
(any_extend:V4SI
(match_operand:V4HI 1 "memory_operand" "m,m,m")))]
and Failed to match this instruction
(set (reg:V4SI 88)
(sign_extend:V4SI (vec_select:V4HI (mem:V8HI (reg:DI 91) [0 *src_3(D)+0 S16
A128])
(parallel [
(const_int 0 [0])
(const_int 1 [0x1])
(const_int 2 [0x2])
(const_int 3 [0x3])
]))))
I doubt the optimization is unsafe since there could be trap in 16-byte load,
but ok for 8-byte load.