[Bug target/102543] -march=cascadelake performs odd alignment peeling

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102543

--- Comment #11 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuho...@gcc.gnu.org>:

https://gcc.gnu.org/g:d3152981f71eef16e50246a94819c39ff1489c70

commit r12-5390-gd3152981f71eef16e50246a94819c39ff1489c70
Author: liuhongt <hongtao....@intel.com>
Date:   Sat Oct 9 09:42:10 2021 +0800

    Reduce cost of aligned sse register store.

    Make them be equal to cost of unaligned ones to avoid odd alignment
    peeling.

    Impact for SPEC2017 on CLX:
    fprate:
      503.bwaves_r    BuildSame
      507.cactuBSSN_r     -0.22
      508.namd_r          -0.02
      510.parest_r        -0.28
      511.povray_r        -0.20
      519.lbm_r       BuildSame
      521.wrf_r           -0.58
      526.blender_r       -0.30
      527.cam4_r           1.07
      538.imagick_r        0.01
      544.nab_r           -0.09
      549.fotonik3d_r BuildSame
      554.roms_r      BuildSame
    intrate:
      500.perlbench_r     -0.25
      502.gcc_r           -0.15
      505.mcf_r       BuildSame
      520.omnetpp_r        1.03
      523.xalancbmk_r     -0.13
      525.x264_r          -0.05
      531.deepsjeng_r     -0.27
      541.leela_r         -0.24
      548.exchange2_r     -0.06
      557.xz_r            -0.10
      999.specrand_ir      2.69

    gcc/ChangeLog:

            PR target/102543
            * config/i386/x86-tune-costs.h (skylake_cost): Reduce cost of
            storing 256/512-bit SSE register to be equal to cost of
            unaligned store to avoid odd alignment peeling.
            (icelake_cost): Ditto.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr102543.c: New test.