https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102860

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2021-10-21
          Component|target                      |middle-end

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
We are expanding

vect__5.73_271 = vect__4.72_269 %[fl] { 39, 39, 39, 39 };

produced from vectorizing

  _5 = _4 %[fl] 39;

optab_for_tree_code does

    case TRUNC_MOD_EXPR:
    case CEIL_MOD_EXPR:
    case FLOOR_MOD_EXPR:
    case ROUND_MOD_EXPR:
      return TYPE_UNSIGNED (type) ? umod_optab : smod_optab;

somehow the vectorizer finds an optab to vectorize this but RTL expansion
fails up to

        /* No luck with division elimination or divmod.  Have to do it
           by conditionally adjusting op0 *and* the result.  */

expand_divmod never seems to use smod_optab for FLOOR_MOD_EXPR.

So this seems to be a latent issue but definitely this expansion code
doing compare & jump has to be gated on !VECTOR_TYPE since do_cmp_and_jump
cannot work with vector arguments.  And then there's a fallback missing
I guess.  Simply gating produces

(insn 35 34 36 (set (reg:V4SI 238)
        (const_vector:V4SI [
                (const_int -52 [0xffffffffffffffcc]) repeated x4
            ])) "simd2.f90":11:30 -1
     (nil))

(insn 36 35 37 (set (reg:V4SI 237 [ vect__4.72 ])
        (plus:V4SI (reg:V4SI 181 [ vect_vec_iv_.68 ])
            (reg:V4SI 238))) "simd2.f90":11:30 -1
     (nil))

(insn 37 36 38 (set (reg:V4SI 240)
        (reg:V4SI 239)) "simd2.f90":11:30 -1
     (nil))

(insn 38 37 39 (set (reg:V4SI 242)
        (const_vector:V4SI [
                (const_int 2 [0x2]) repeated x4
            ])) "simd2.f90":11:30 -1
     (nil))

(insn 39 38 40 (set (reg:V4SI 241)
        (ashift:V4SI (reg:V4SI 240)
            (reg:V4SI 242))) "simd2.f90":11:30 -1
     (nil))

(insn 40 39 41 (set (reg:V4SI 240)
        (reg:V4SI 241)) "simd2.f90":11:30 -1
     (nil))

(insn 41 40 42 (set (reg:V4SI 243)
        (plus:V4SI (reg:V4SI 240)
            (reg:V4SI 239))) "simd2.f90":11:30 -1
     (nil))

(insn 42 41 43 (set (reg:V4SI 245)
        (const_vector:V4SI [
                (const_int 3 [0x3]) repeated x4
            ])) "simd2.f90":11:30 -1
     (nil))

(insn 43 42 44 (set (reg:V4SI 244)
        (ashift:V4SI (reg:V4SI 243)
            (reg:V4SI 245))) "simd2.f90":11:30 -1
     (nil))

(insn 44 43 45 (set (reg:V4SI 243)
        (reg:V4SI 244)) "simd2.f90":11:30 -1
     (nil))

(insn 45 44 46 (set (reg:V4SI 246)
        (minus:V4SI (reg:V4SI 243)
            (reg:V4SI 239))) "simd2.f90":11:30 -1
     (nil))

(insn 46 45 0 (set (reg:V4SI 221 [ vect__5.73 ])
        (minus:V4SI (reg:V4SI 237 [ vect__4.72 ])
            (reg:V4SI 246))) "simd2.f90":11:30 -1
     (nil))

which I guess is OK for trunc_mod but not floor_mod, but it fixes the ICE.

diff --git a/gcc/expmed.c b/gcc/expmed.c
index bbdd0e71d20..0ae57cc3f8a 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -4850,7 +4850,7 @@ expand_divmod (int rem_flag, enum tree_code code,
machine_mode mode,

        /* No luck with division elimination or divmod.  Have to do it
           by conditionally adjusting op0 *and* the result.  */
-       {
+       if (!VECTOR_MODE_P (mode)) {
          rtx_code_label *label1, *label2, *label3, *label4, *label5;
          rtx adjusted_op0;
          rtx tem;


The floor-mod is present in .original already:

simd2.f90.005t.original:        b[(integer(kind=8)) i + -1] = (i + -52) %[fl]
39;

looks like the modulo intrinsic is floor_mod?

    b(i) = modulo (i - 52, 39)

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