https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85730
--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> ---
(In reply to Richard Biener from comment #5)
> The GIMPLE IL is now using BIT_INSERT_EXPRs consistently for all cases and
> combine does
>
> Trying 8 -> 11:
> 8: {r90:SI=r89:SI<<0x1;clobber flags:CC;}
> REG_DEAD r89:SI
> REG_UNUSED flags:CC
> 11: strict_low_part(r92:V4QI#0)=r90:SI#0
> REG_DEAD r90:SI
> Failed to match this instruction:
> (set (strict_low_part (subreg:QI (reg:V4QI 92 [ v ]) 0))
> (ashift:QI (subreg:QI (reg:SI 89 [ v ]) 0)
> (const_int 1 [0x1])))
>
> where it fails to try (add:QI (subreg...) (subreg...)) instead of the shift
> by 1.
>
> Not sure whether targets should have a special-case pattern here or whether
> that's for combine to un-canonicalize it?
We do have this pattern in i386.md, but please see the FIXME:
(define_insn "*ashl<mode>3_1_slp"
[(set (strict_low_part (match_operand:SWI12 0 "register_operand" "+<r>"))
(ashift:SWI12 (match_operand:SWI12 1 "register_operand" "0")
(match_operand:QI 2 "nonmemory_operand" "cI")))
(clobber (reg:CC FLAGS_REG))]
"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
/* FIXME: without this LRA can't reload this pattern, see PR82524. */
&& rtx_equal_p (operands[0], operands[1])"
