https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71775
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Ever confirmed|0 |1
Status|UNCONFIRMED |NEW
Severity|normal |enhancement
Component|target |rtl-optimization
Keywords| |missed-optimization
Last reconfirmed| |2021-08-07
--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed:
Trying 11 -> 13:
11: {r87:DI=ctz(r86:DI);clobber flags:CC;}
REG_UNUSED flags:CC
13: r88:DI=sign_extend(r87:DI#0)
REG_DEAD r87:DI
Failed to match this instruction:
(set (reg:DI 88 [ _1 ])
(sign_extend:DI (subreg:SI (ctz:DI (reg/v:DI 86 [ x ])) 0)))
Part of the problem is ctz has an unkown value at 0 but we know x is non-zero
(well kinda, at the gimple level we do).
We do the right thing on aarch64 because we know the value at 0.
Trying 11 -> 13:
11: r97:DI=ctz(r96:DI)
13: r98:DI=sign_extend(r97:DI#0)
REG_DEAD r97:DI
Successfully matched this instruction:
(set (reg:DI 98 [ _1 ])
(ctz:DI (reg/v:DI 96 [ x ])))
allowing combination of insns 11 and 13
original costs 8 + 4 = 12
replacement cost 8
deferring deletion of insn with uid = 11.
modifying insn i3 13: r98:DI=ctz(r96:DI)
deferring rescan insn with uid = 13.
So this requires us to bring the range down from gimple to RTL.
Here is the range:
# RANGE [1, 18446744073709551615]
# x_12 = PHI <x_10(3), x_6(D)(2)>
