https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101787
Hongtao.liu <crazylht at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|RESOLVED |REOPENED
Resolution|FIXED |---
--- Comment #4 from Hongtao.liu <crazylht at gmail dot com> ---
+@samp{cond_@var{op}@var{mode}} generally corresponds to a conditional
+form of @samp{@var{op}@var{mode}3}. As an exception, the vector forms
+of shifts correspond to patterns like @code{vashl@var{mode}3} rather
+than patterns like @code{ashl@var{mode}3}.
It seems it supports both vashl and ashl
ashl with immediate shift count.
<bb 3> [local count: 139586405]:
# ivtmp.27_5 = PHI <ivtmp.27_12(3), 0(2)>
vect__1.9_34 = MEM <vector(8) int> [(int *)&b + ivtmp.27_5 * 1];
vect__2.12_37 = MEM <vector(8) int> [(int *)&c + ivtmp.27_5 * 1];
vect_pretmp_13.15_40 = MEM <vector(8) int> [(int *)&d + ivtmp.27_5 * 1];
vect__6.19_44 = MEM <vector(8) int> [(int *)&e + ivtmp.27_5 * 1];
vect__7.20_45 = MAX_EXPR <vect_pretmp_13.15_40, vect__6.19_44>;
_46 = vect__1.9_34 < vect__2.12_37;
_33 = .COND_SHL (_46, vect_pretmp_13.15_40, 3, vect__7.20_45);
MEM <vector(8) int> [(int *)&a + ivtmp.27_5 * 1] = _33;
ashl with variable shift count:
<bb 2> [local count: 10737416]:
_4 = e[0];
<bb 3> [local count: 139586405]:
# ivtmp.98_6 = PHI <ivtmp.98_13(3), 0(2)>
vect__1.80_35 = MEM <vector(8) int> [(int *)&b + ivtmp.98_6 * 1];
vect__2.83_38 = MEM <vector(8) int> [(int *)&c + ivtmp.98_6 * 1];
vect_pretmp_14.86_41 = MEM <vector(8) int> [(int *)&d + ivtmp.98_6 * 1];
vect__7.90_45 = MEM <vector(8) int> [(int *)&e + ivtmp.98_6 * 1];
vect__8.91_46 = MAX_EXPR <vect_pretmp_14.86_41, vect__7.90_45>;
_47 = vect__1.80_35 < vect__2.83_38;
_34 = .COND_SHL (_47, vect_pretmp_14.86_41, _4, vect__8.91_46);
MEM <vector(8) int> [(int *)&a + ivtmp.98_6 * 1] = _34;
ivtmp.98_13 = ivtmp.98_6 + 32;
vashl with vector shift count:
<bb 3> [local count: 139586405]:
# ivtmp.98_6 = PHI <ivtmp.98_13(3), 0(2)>
vect__1.80_34 = MEM <vector(8) int> [(int *)&b + ivtmp.98_6 * 1];
vect__2.83_37 = MEM <vector(8) int> [(int *)&c + ivtmp.98_6 * 1];
vect_pretmp_14.86_40 = MEM <vector(8) int> [(int *)&d + ivtmp.98_6 * 1];
vect_pretmp_18.89_43 = MEM <vector(8) int> [(int *)&e + ivtmp.98_6 * 1];
vect__8.91_45 = MAX_EXPR <vect_pretmp_14.86_40, vect_pretmp_18.89_43>;
_46 = vect__1.80_34 < vect__2.83_37;
_33 = .COND_SHL (_46, vect_pretmp_14.86_40, vect_pretmp_18.89_43,
vect__8.91_45);
MEM <vector(8) int> [(int *)&a + ivtmp.98_6 * 1] = _33;
ivtmp.98_13 = ivtmp.98_6 + 32;
