https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101205
--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The problem is csinv3si_insn, csinv3_uxtw_insn2, nor csinv3_uxtw_insn3 would
match as those have the zero_extend inside the if/then/else rather on the
outside which is being matched here:
Trying 36 -> 19:
36: r94:SI={(cc:CC==0)?~r100:SI:r101:SI}
REG_DEAD r100:SI
REG_DEAD cc:CC
REG_DEAD r101:SI
19: x0:DI=zero_extend(r94:SI)
REG_DEAD r94:SI
Failed to match this instruction:
(set (reg/i:DI 0 x0)
(zero_extend:DI (if_then_else:SI (eq (reg:CC 66 cc)
(const_int 0 [0]))
(not:SI (reg:SI 100))
(reg:SI 101))))
