https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101325
--- Comment #12 from Christophe Lyon <clyon at gcc dot gnu.org> ---
As I am going on holidays until August (back only 2 days until then), I thought
I should share my WIP here. No sure that's the right direction, anyway that's
not working yet.
a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index fa0fb0b..cf2c9b8 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -1633,6 +1633,10 @@ arm_init_simd_builtin_types (void)
arm_simd_types[Bfloat16x4_t].eltype = arm_bf16_type_node;
arm_simd_types[Bfloat16x8_t].eltype = arm_bf16_type_node;
+ arm_simd_types[Pred1x16_t].eltype = unsigned_intHI_type_node;
+ arm_simd_types[Pred2x8_t].eltype = unsigned_intHI_type_node;
+ arm_simd_types[Pred4x4_t].eltype = unsigned_intHI_type_node;
+
for (i = 0; i < nelts; i++)
{
tree eltype = arm_simd_types[i].eltype;
diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def
index a5e74ba..098831c 100644
--- a/gcc/config/arm/arm-modes.def
+++ b/gcc/config/arm/arm-modes.def
@@ -84,6 +84,15 @@ VECTOR_MODE (FLOAT, BF, 2); /* V2BF. */
VECTOR_MODE (FLOAT, BF, 4); /* V4BF. */
VECTOR_MODE (FLOAT, BF, 8); /* V8BF. */
+/* Predicates for MVE. */
+VECTOR_BOOL_MODE (VNx16BI, 16, 2);
+VECTOR_BOOL_MODE (VNx8BI, 8, 2);
+VECTOR_BOOL_MODE (VNx4BI, 4, 2);
+
+ADJUST_NUNITS (VNx16BI, arm_vg * 8);
+ADJUST_NUNITS (VNx8BI, arm_vg * 4);
+ADJUST_NUNITS (VNx4BI, arm_vg * 2);
+
/* Fraction and accumulator vector modes. */
VECTOR_MODES (FRACT, 4); /* V4QQ V2HQ */
VECTOR_MODES (UFRACT, 4); /* V4UQQ V2UHQ */
diff --git a/gcc/config/arm/arm-simd-builtin-types.def
b/gcc/config/arm/arm-simd-builtin-types.def
index c19a1b6..6a5053f 100644
--- a/gcc/config/arm/arm-simd-builtin-types.def
+++ b/gcc/config/arm/arm-simd-builtin-types.def
@@ -51,3 +51,7 @@
ENTRY (Bfloat16x2_t, V2BF, none, 32, bfloat16, 20)
ENTRY (Bfloat16x4_t, V4BF, none, 64, bfloat16, 20)
ENTRY (Bfloat16x8_t, V8BF, none, 128, bfloat16, 20)
+
+ ENTRY (Pred1x16_t, VNx16BI, unsigned, 16, uint16, 21)
+ ENTRY (Pred2x8_t, VNx8BI, unsigned, 8, uint16, 21)
+ ENTRY (Pred4x4_t, VNx4BI, unsigned, 4, uint16, 21)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index f967239..98ff238 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3446,6 +3446,8 @@ arm_configure_build_target (struct arm_build_target
*target,
arm_option_reconfigure_globals ();
}
+poly_uint16 arm_vg;
+
/* Fix up any incompatible options that the user has specified. */
static void
arm_option_override (void)
@@ -3458,6 +3460,7 @@ arm_option_override (void)
static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS,
isa_nobit};
cl_target_option opts;
+ arm_vg = 2;
isa_quirkbits = sbitmap_alloc (isa_num_bits);
arm_initialize_isa (isa_quirkbits, quirk_bitlist);
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 8e5bd57..df9bbb2 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -2493,4 +2493,7 @@ const char *arm_be8_option (int argc, const char **argv);
representation for SHF_ARM_PURECODE in GCC. */
#define SECTION_ARM_PURECODE SECTION_MACH_DEP
+#ifndef USED_FOR_TARGET
+extern poly_uint16 arm_vg;
+#endif
#endif /* ! GCC_ARM_H */
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index 83f1003..765ec5a 100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -3524,7 +3524,7 @@ __arm_vaddlvq_u32 (uint32x4_t __a)
return __builtin_mve_vaddlvq_uv4si (__a);
}
-__extension__ extern __inline int64_t
+__extension__ extern __inline mve_pred16_t/*int64_t*/
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
__arm_vctp16q (uint32_t __a)
{
diff --git a/gcc/config/arm/arm_mve_types.h b/gcc/config/arm/arm_mve_types.h
index 8958f4e..536e816 100644
--- a/gcc/config/arm/arm_mve_types.h
+++ b/gcc/config/arm/arm_mve_types.h
@@ -34,7 +34,8 @@ typedef struct { float32x4_t val[2]; } float32x4x2_t;
typedef struct { float32x4_t val[4]; } float32x4x4_t;
#endif
-typedef uint16_t mve_pred16_t;
+//typedef uint16_t mve_pred16_t;
+typedef __simd16_uint16_t mve_pred16_t;
typedef __simd128_uint8_t uint8x16_t;
typedef __simd128_uint16_t uint16x8_t;
typedef __simd128_uint32_t uint32x4_t;
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 5c4fe89..2656f6b 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -948,6 +948,8 @@ (define_mode_attr V_extr_elem [(V16QI "u8") (V8HI "u16")
(V4SI "32")
(V8HF "u16") (V4SF "32")])
(define_mode_attr earlyclobber_32 [(V16QI "=w") (V8HI "=w") (V4SI "=&w")
(V8HF "=w") (V4SF "=&w")])
+;;(define_mode_attr MVE_VPRED [(V16QI "VNx16BI") (V8HI "VNx8BI") (V4SI
"VNx4BI")])
+(define_mode_attr MVE_VPRED [(V16QI "VNx16BI") (V8HI "VNx16BI") (V4SI
"VNx16BI") (V8HF "VNx16BI") (V4SF "VNx16BI")])
;;----------------------------------------------------------------------------
;; Code attributes
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index a984040..0052bd5 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -130,7 +130,7 @@ (define_insn "mve_vrndq_m_f<mode>"
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:MVE_0 2 "s_register_operand" "w")
- (match_operand:HI 3 "vpr_register_operand" "Up")]
+ (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
VRNDQ_M_F))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
@@ -658,8 +658,8 @@ (define_insn "mve_vaddlvq_<supf>v4si"
;;
(define_insn "mve_vctp<mode1>qhi"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
+ (set (match_operand:VNx16BI 0 "vpr_register_operand" "=Up")
+ (unspec:VNx16BI [(match_operand:SI 1 "s_register_operand" "r")]
VCTPQ))
]
"TARGET_HAVE_MVE"
@@ -672,8 +672,8 @@ (define_insn "mve_vctp<mode1>qhi"
;;
(define_insn "mve_vpnothi"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")]
+ (set (match_operand:VNx16BI 0 "vpr_register_operand" "=Up")
+ (unspec:VNx16BI [(match_operand:VNx16BI 1 "vpr_register_operand" "0")]
VPNOT))
]
"TARGET_HAVE_MVE"
[....]
@@ -839,8 +839,8 @@ (define_insn "mve_vaddlvq_p_<supf>v4si"
;;
(define_insn "@mve_vcmp<mve_cmp_op>q_<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (MVE_COMPARISONS:<MVE_VPRED> (match_operand:MVE_2 1
"s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")))
]
"TARGET_HAVE_MVE"
@@ -853,8 +853,8 @@ (define_insn "@mve_vcmp<mve_cmp_op>q_<mode>"
;;
(define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>"
[
- (set (match_operand:HI 0 "vpr_register_operand" "=Up")
- (MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w")
+ (set (match_operand:<MVE_VPRED> 0 "vpr_register_operand" "=Up")
+ (MVE_COMPARISONS:<MVE_VPRED> (match_operand:MVE_2 1
"s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")))
]
"TARGET_HAVE_MVE"
but that requires lots of changes to mve.md, everywhere vpr_register_operand is
involved.
Besides, this means that vcmp* now return a vector instead of a scalar.
