https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101185
--- Comment #6 from Uroš Bizjak <ubizjak at gmail dot com> --- (In reply to Richard Biener from comment #5) > Of course I wonder why the RA even chooses registers that are not available > on the architecture. I suppose there's no real way to turn regs on/off but > the way is to make them never match any instruction pattern and thus give RA > no incentive to use them? That is, why was kmovd %edx,%k0 deemed a valid > recognizable instruction? RA is not problematic here, because registers are available due to -mavx512f. The problem is that due to the register pressure around cpuid insn on 32bit targets RA chooses to move the value to the mask register. cpuid and the logic around is used to determine if avx512f is supported on the runtime target, and mask instructions acting as logic instructions around cpuid causes SIGILL in case avx512 is not supported during execution. The solution to this is to allocate mask registers last and raise the cost of moves from GPR to mask regs, so (similar to MMX) mask regs are only used when absolutely necessary. In the past, I have introduced separate instruction patterns, instanced exclusively from builtins, but they didn't support generic logic operators, e.g. "mask1 & mask2". To solve this, mask reg alternatives were added to standard logic patterns, so there is now no clear cut between mask and GPR alternatives.
