[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[clyon at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #10 from Christophe Lyon <clyon at gcc dot gnu.org> ---
The problem is in vec-common.md:
(define_expand "vcond_mask_<mode><v_cmp_result>"
  [(set (match_operand:VDQWH 0 "s_register_operand")
        (if_then_else:VDQWH
          (match_operand:<V_cmp_result> 3 "s_register_operand")
          (match_operand:VDQWH 1 "s_register_operand")
          (match_operand:VDQWH 2 "s_register_operand")))]
  "ARM_HAVE_<MODE>_ARITH
   && !TARGET_REALLY_IWMMXT
   && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
{
  if (TARGET_NEON)
    {
      emit_insn (gen_neon_vbsl (<MODE>mode, operands[0], operands[3],
                                operands[1], operands[2]));
    }
  else if (TARGET_HAVE_MVE)
    {
      emit_insn (gen_mve_vpselq (VPSELQ_S, <MODE>mode, operands[0],
                                 operands[1], operands[2], operands[3]));
    }
  else
    gcc_unreachable ();
  DONE;
})

For MVE, we pass operands[3] to mve_vpselq, but it has the same vector mode as
the other operands while vpselq expects a 16-bit mask (HI mode) suitable for
VPR.P0