https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100265
Bug ID: 100265
Summary: [RISCV] Use proper fences for atomic load/store
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: christophm30 at gmail dot com
Target Milestone: ---
On RISC-V we don't have load/store instructions with memory ordering bits.
To enforce memory ordering we need to use FENCE instructions.
The good thing is, we can have support for sub-word load/store.
The particular FENCE arguments (i.e. how to map the C ordering to RISC-V
ordering is documented in the RISC-V unpriv spec in section "Code Porting and
Mapping Guidelines").
Currenlty, GCC generates the following:
load_u32_n:
lw a0,0(a0)
sext.w a0,a0
ret
load_u32_aq_n:
lw a0,0(a0)
fence iorw,iorw
sext.w a0,a0
ret
store_u32_n:
amoswap.w zero,a1,0(a0)
ret
store_u32_rl_n:
fence iorw,ow
amoswap.w zero,a1,0(a0)
ret
The goal would be to generate this as follows:
load_u32_n:
lw a0,0(a0)
ret
load_u32_aq_n:
lw a0,0(a0)
fence r,rw
ret
store_au32_n:
sw a1,0(a0)
ret
store_au32_rl_n:
fence rw,w
sw a1,0(a0)
ret
