https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99842
Peter Bergner <bergner at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Target| |powerpc64le-linux
Ever confirmed|0 |1
Known to fail| |11.0
Assignee|unassigned at gcc dot gnu.org |bergner at gcc dot
gnu.org
Last reconfirmed| |2021-03-30
Status|UNCONFIRMED |ASSIGNED
Target Milestone|--- |11.0
--- Comment #1 from Peter Bergner <bergner at gcc dot gnu.org> ---
Mine. The problem is that the mma_assemble_input_operand predicate is
rejecting valid reg+reg indexed addresses in the MEMs in the above rtl. The
predicate is calling quad_address_p() which accepts reg+offset addresses (with
constrained offset values), but doesn't allow reg+reg addresses, which are
valid.
Replacing the MEM_P() && quad_address_p() test with a call to memory_operand()
fixes the ICE, since it calls down to rs6000_legitimate_address_p(), which
calls quad_address_p() to validate reg+offset addresses, but also allows
reg+reg addresses. I'll submit a patch with that fix.
