[Bug target/99822] [11 Regression] Assembler messages: Error: integer register expected in the extended/shifted operand register at operand 3 -- `adds x1,xzr,#2'

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99822

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkac...@gcc.gnu.org>:

https://gcc.gnu.org/g:19199a6f2b0f4ce4b100856c78706d56a16b1956

commit r11-7912-g19199a6f2b0f4ce4b100856c78706d56a16b1956
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date:   Tue Mar 30 15:43:36 2021 +0100

    aarch64: PR target/99822 Don't allow zero register in first operand of
SUBS/ADDS-immediate

    In this PR we end up generating an invalid instruction:
    adds x1,xzr,#2

    because the pattern accepts zero as an operand in the comparison, but the
instruction doesn't.
    Fix it by adjusting the predicate and constraints.

    gcc/ChangeLog:

            PR target/99822
            * config/aarch64/aarch64.md (sub<mode>3_compare1_imm): Do not allow
zero
            in operand 1.

    gcc/testsuite/ChangeLog:

            PR target/99822
            * gcc.c-torture/compile/pr99822.c: New test.