[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy() since g:d9f0ade001533c9544bf2153b6baa8844ec0bee4

[cvs-commit at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kito Cheng <k...@gcc.gnu.org>:

https://gcc.gnu.org/g:e1aa525179b72fb7ea7822c794ec844893ed47e4

commit r10-9506-ge1aa525179b72fb7ea7822c794ec844893ed47e4
Author: Kito Cheng <kito.ch...@sifive.com>
Date:   Mon Mar 22 16:32:45 2021 +0800

    PR target/99702: Check RTL type before get value

    gcc/ChangeLog:

            PR target/99702
            * config/riscv/riscv.c (riscv_expand_block_move): Get RTL value
            after type checking.

    gcc/testsuite/ChangeLog:

            PR target/99702
            * gcc.target/riscv/pr99702.c: New.

    (cherry picked from commit 540dace2ed3949571f2ce6cb007354e69bda0cb2)