https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99092
--- Comment #11 from Iain Sandoe <iains at gcc dot gnu.org> --- (In reply to Andrew Pinski from comment #10) > From the ARM ARM: > An assembler program translating a Load/Store instruction, for example LDR, > is required to encode an unambiguous offset using the unscaled 9-bit offset > form, and to encode an ambiguous offset using the scaled 12-bit offset form. > A programmer might force the generation of the unscaled 9-bit form by using > one of the mnemonics in Table C3-17. Arm recommends that a disassembler > outputs all unscaled 9-bit offset forms using one of these mnemonics, but > unambiguous offsets can be output using a Load/Store single register > mnemonic, for example, LDR. it would be nice if that applied to a 'generic' version of the insn (one might read the advice as so): prf PLDL1KEEP, [x0, 200] ===> assembler chooses prfm/prfum as it likes prfm PLDL1KEEP, [x0, 200] --> use the insn I wrote! prfm PLDL1KEEP, [x0, -8] --> .. or error if I'm dumb prfum PLDL1KEEP, [x0, 200] --> use the insn I wrote! prfum PLDL1KEEP, [x0, 4096] --> .. or error if I'm dumb .... but I guess we have to live with the status quo.
