https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98833

--- Comment #1 from Hongtao.liu <crazylht at gmail dot com> ---
hmm, why TARGET_SSE2 && !TARGET_XOP?

(define_insn "*sse2_eq<mode>3"
  [(set (match_operand:VI124_128 0 "register_operand" "=x,x")
        (eq:VI124_128
          (match_operand:VI124_128 1 "vector_operand" "%0,x")
          (match_operand:VI124_128 2 "vector_operand" "xBm,xm")))]
  "TARGET_SSE2 && !TARGET_XOP
   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"

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