https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98799
luoxhu at gcc dot gnu.org changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |luoxhu at gcc dot gnu.org
--- Comment #5 from luoxhu at gcc dot gnu.org ---
(In reply to David Edelsohn from comment #4)
> Created attachment 50043 [details]
> patch
>
> Updated patch, but the entire rs6000_expand_set_var() logic seems to be
> incomplete and missing some scenarios, i.e., P9 and P8 that assume PPC64 are
> not sufficient.
The ICE is caused by UNSPEC_SI_FROM_SF not supported when
TARGET_DIRECT_MOVE_64BIT
is false.
Thank for the patch, but also need below change to fix the ICE in
gcc.target/powerpc/fold-vec-insert-float-p8.c when build with -m32 to avoid
generate IFN VEC_SET for P8BE-32bit.
Not sure about the meaning of "P9 and P8 that assume PPC64 are not sufficient"?
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index f6ee1e6..656cdb3 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -1600,7 +1600,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree
fndecl,
stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt);
}
- if (TARGET_P8_VECTOR)
+ if (TARGET_P8_VECTOR && TARGET_DIRECT_MOVE_64BIT)
{
stmt = build_array_ref (loc, stmt, arg2);
stmt = fold_build2 (MODIFY_EXPR, TREE_TYPE (arg0), stmt,
