https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98759
Bug ID: 98759
Summary: arm cortex-r5 single precisions flotaing point
generation
Product: gcc
Version: 10.2.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: dallred at tesla dot com
Target Milestone: ---
Created attachment 50008
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=50008&action=edit
Simple source file for replication
Trying to compile the simple floating point C function in the attached C file,
for an embedded Cortex-R5F core that does not support double precision in the
VFPv3, to an object file using either of the following:
$ arm-none-eabi-gcc -mcpu=cortex-r5+nofp.dp -mfloat-abi=hard -o float-test.o -c
float-test.c
$ arm-none-eabi-gcc -march=armv7-r+vfpv3xd -mfloat-abi=hard -o float-test.o -c
float-test.c
These two commands should be equivalent, and are, but they both fail at the
assembly step with a message like the following:
tmp/cc5XbvoO.s: Assembler messages:
/tmp/cc5XbvoO.s:42: Error: selected processor does not support `vmul.f32
s15,s14,s15' in ARM mode
The -mfloat-abi can be either 'hard' or 'softfp', result is the same. This was
observed using the prepackaged GCC downloads for Cortex-R/M made available by
ARM:
https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads
This issue is observed using both gcc-arm-none-eabi-10-2020-q4-major and
gcc-arm-none-eabi-9-2020-q2-update. To me, it seems the generated assembly is
correct. I can't fathom why the assembler is complaining and I don't know why
it is saying this instruction is not supported in ARM mode. Interestingly,
using the -mthumb flag does allow the compilation to object file succeed. I can
find no evidence of VFP instructions being restricted to either ARM or Thumb2
mode of the processor.
