[Bug target/98196] [11 Regression] aarch64: Wrong code at -O3 -march=armv8.2-a+sve -msve-vector-bits=256 -fvect-cost-model=unlimited

[rguenth at gcc dot gnu.org via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=98196

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |11.0
          Component|tree-optimization           |target

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
The only thing we "sink" is

Sinking _37 = (long int) _36;
 from bb 4 to bb 5

that makes the loop look like

  <bb 4> [local count: 536870913]:
  # g_23 = PHI <g_22(9), 0(8)>
  _32 = (long unsigned int) g_23;
  _33 = _32 * 11;
  _34 = &c + _33;
  _36 = (*_34)[0];
  g_22 = g_23 + 4;
  if (g_22 != 16)
    goto <bb 9>; [75.00%]
  else
    goto <bb 5>; [25.00%]

  <bb 9> [local count: 402653181]:
  goto <bb 4>; [100.00%]

  <bb 5> [local count: 134217731]:
  _37 = (long int) _36;
  b = _37;

we use a gather load for vectorization:

  vect__36.12_1 = .GATHER_LOAD (vectp_c.10_6, { 0, 44, 88, 132 }, 1, { 0, 0, 0,
0 });

I suspect that is somehow expanded badly:

(insn 78 77 0 (set (reg:VNx2QI 92 [ vect__36.12 ])
        (unspec:VNx2QI [
                (subreg:VNx2BI (reg:VNx16BI 154) 0)
                (reg/f:DI 150)
                (reg:VNx2DI 152)
                (const_int 1 [0x1]) repeated x2
                (mem:BLK (scratch) [0  A8])
            ] UNSPEC_LD1_GATHER)) "t.c":12:15 -1
     (nil))

not aliasing with the stores which look like

(insn 33 32 34 (set (reg:DI 121)
        (high:DI (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]))) "t.c":9:15 -1
     (nil))

(insn 34 33 35 (set (reg/f:DI 120)
        (lo_sum:DI (reg:DI 121)
            (symbol_ref:DI ("*.LANCHOR0") [flags 0x182]))) "t.c":9:15 -1
     (expr_list:REG_EQUAL (symbol_ref:DI ("*.LANCHOR0") [flags 0x182])
        (nil)))

(insn 36 35 0 (set (mem/c:QI (plus:DI (reg/f:DI 120)
                (const_int 77 [0x4d])) [0 MEM[(signed char *)&c + 77B]+0 S1
A8])
        (reg:QI 122)) "t.c":9:15 -1
     (nil))

maybe due to the section anchor.