[Bug other/97417] RISC-V Unnecessary andi instruction when loading volatile bool

[admin at levyhsu dot com via Gcc-bugs]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417

--- Comment #19 from Levy <admin at levyhsu dot com> ---
Also tested code without int extend, just zero-extend with unsignedp set to 1,
Still seg fault.

if (GET_MODE_CLASS (mode) == MODE_INT
              && GET_MODE_SIZE (mode) < UNITS_PER_WORD
        && can_create_pseudo_p()
        && MEM_P (src))
  {
    rtx temp_reg = force_reg (word_mode, convert_to_mode (word_mode, src, 1));
    riscv_emit_move(dest, temp_reg);
    return true;
  }