https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97417
Jim Wilson <wilson at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |wilson at gcc dot gnu.org
Status|UNCONFIRMED |NEW
Last reconfirmed| |2020-10-15
Ever confirmed|0 |1
--- Comment #1 from Jim Wilson <wilson at gcc dot gnu.org> ---
Comparing with the ARM port, I see that in the ARM port, the movqi pattern
emits
(insn 8 7 9 2 (set (reg:SI 117)
(zero_extend:SI (mem/v/c:QI (reg/f:SI 115) [1 active+0 S1 A8])))
"tmp.c\
":7:7 -1
(nil))
(insn 9 8 10 2 (set (reg:QI 116)
(subreg:QI (reg:SI 117) 0)) "tmp.c":7:7 -1
(nil))
and then later it combines the subreg operation with the following zero_extend
and cancels them out.
Whereas in the RISC-V port, the movqi pattern emits
(insn 9 7 10 2 (set (reg:QI 76)
(mem/v/c:QI (lo_sum:DI (reg:DI 74)
(symbol_ref:DI ("active") [flags 0xc4] <var_decl
0x7f9f0310312\
0 active>)) [1 active+0 S1 A8])) "tmp.c":7:7 -1
(nil))
and then combine refuses to combine the following zero-extend with this insn as
the memory operation is volatile.
So it seems we need to rewrite the RISC-V port to make movqi and movhi zero
extend to si/di mode and then subreg. That probably will require cascading
changes to avoid code size and performance regressions.
Looks like a tractable small to medium size project, but will need to wait for
a volunteer to work on it.
