[Bug target/71233] [ARM, AArch64] missing AdvSIMD intrinsics

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71233

--- Comment #31 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkac...@gcc.gnu.org>:

https://gcc.gnu.org/g:30957092db46d8798e632feefb5df634488dbb33

commit r11-3354-g30957092db46d8798e632feefb5df634488dbb33
Author: Kyrylo Tkachov <kyrylo.tkac...@arm.com>
Date:   Tue Sep 22 12:03:49 2020 +0100

    AArch64: Implement missing vcls intrinsics on unsigned types

    This patch implements some missing intrinsics that perform a CLS on
unsigned SIMD types.

    Bootstrapped and tested on aarch64-none-linux-gnu.

    gcc/
            PR target/71233
            * config/aarch64/arm_neon.h (vcls_u8, vcls_u16, vcls_u32,
            vclsq_u8, vclsq_u16, vclsq_u32): Define.

    gcc/testsuite/
            PR target/71233
            * gcc.target/aarch64/simd/vcls_unsigned_1.c: New test.