https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88345
Koen Zandberg <koen.zandberg at inria dot fr> changed:
What |Removed |Added
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CC| |koen.zandberg at inria dot fr
--- Comment #6 from Koen Zandberg <koen.zandberg at inria dot fr> ---
We're hitting this bug on the an ARMv7 (cortex-m7) platform. Due to cache
alignment we see a significant increase in performance when aligning individual
functions on cache line boundaries, but we still prefer to compile with size
optimizations enabled due to the limited resources available on the platform.
Is there a way to work around this issue and enable -falign-functions together
with -Os?
