https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96581
Bug ID: 96581
Summary: aarch64:ICE during GIMPLE pass: veclower
Product: gcc
Version: 11.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: z.zhanghaijian at huawei dot com
Target Milestone: ---
For aarch64 SVE,
The case:
typedef unsigned char v32u8 __attribute__ ((vector_size (32)));
unsigned __attribute__((noinline, noclone))
foo(unsigned u)
{
v32u8 v32u8_0 = (v32u8){} > (v32u8){-u};
return v32u8_0[31] + v32u8_0[0];
}
This will cause an ICE when compiled with -S -march=armv8.5-a+sve
-msve-vector-bits=512.
By tracing the debug infomation, It is found that the error is caused by the
failure to find the pattern corresponding to CODE_FOR_vcond_mask_vnx8qivnx8bi.
I tried to extend the mode of this pattern from SVE_FULL to SVE_ALL to fix it.
Proposed patch:
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -6722,11 +6722,11 @@ (define_insn "@aarch64_sve_<sve_fp_op><mode>"
;; UNSPEC_SEL operand order: mask, true, false (as for VEC_COND_EXPR)
;; SEL operand order: mask, true, false
(define_expand "@vcond_mask_<mode><vpred>"
- [(set (match_operand:SVE_FULL 0 "register_operand")
- (unspec:SVE_FULL
+ [(set (match_operand:SVE_ALL 0 "register_operand")
+ (unspec:SVE_ALL
[(match_operand:<VPRED> 3 "register_operand")
- (match_operand:SVE_FULL 1 "aarch64_sve_reg_or_dup_imm")
- (match_operand:SVE_FULL 2 "aarch64_simd_reg_or_zero")]
+ (match_operand:SVE_ALL 1 "aarch64_sve_reg_or_dup_imm")
+ (match_operand:SVE_ALL 2 "aarch64_simd_reg_or_zero")]
UNSPEC_SEL))]
"TARGET_SVE"
{
@@ -6740,11 +6740,11 @@ (define_expand "@vcond_mask_<mode><vpred>"
;; - a duplicated immediate and a register
;; - a duplicated immediate and zero
(define_insn "*vcond_mask_<mode><vpred>"
- [(set (match_operand:SVE_FULL 0 "register_operand" "=w, w, w, w, ?w, ?&w,
?&w")
- (unspec:SVE_FULL
+ [(set (match_operand:SVE_ALL 0 "register_operand" "=w, w, w, w, ?w, ?&w,
?&w")
+ (unspec:SVE_ALL
[(match_operand:<VPRED> 3 "register_operand" "Upa, Upa, Upa, Upa,
Upl, Upl, Upl")
- (match_operand:SVE_FULL 1 "aarch64_sve_reg_or_dup_imm" "w, vss, vss,
Ufc, Ufc, vss, Ufc")
- (match_operand:SVE_FULL 2 "aarch64_simd_reg_or_zero" "w, 0, Dz, 0,
Dz, w, w")]
+ (match_operand:SVE_ALL 1 "aarch64_sve_reg_or_dup_imm" "w, vss, vss,
Ufc, Ufc, vss, Ufc")
+ (match_operand:SVE_ALL 2 "aarch64_simd_reg_or_zero" "w, 0, Dz, 0,
Dz, w, w")]
UNSPEC_SEL))]
"TARGET_SVE
&& (!register_operand (operands[1], <MODE>mode)
Any suggestions?
