https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95285
--- Comment #13 from Wilco <wilco at gcc dot gnu.org> --- (In reply to Bu Le from comment #11) > > > You're right, we need an extra add, so it's like this: > > > > adrp x0, bar1.2782 > > movk x1, :high32_47:bar1.2782 > > add x0, x0, x1 > > add x0, x0, :lo12:bar1.2782 > > > > > (By the way, the high32_47 relocation you suggested is the prel_g2 in the > > > officail aarch64 ABI released) > > > > It needs a new relocation because of the ADRP. ADR could be used so the > > existing R_<CLS>_MOVW_PREL_G0-3 work, but then you need 5 instructions. > > So you suggest a new relocation type "high32_47" to calculate the offset > between ADRP and bar1. Am I right? Yes. It needs to have an offset to the adrp instruction so it can compute the correct ADRP offset and then extract bits 32-47.
