https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95265
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Keywords| |missed-optimization
Status|UNCONFIRMED |NEW
Depends on| |92665
Severity|normal |enhancement
Last reconfirmed| |2020-05-21
Ever confirmed|0 |1
--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The patch for PR 92665 fixes the dup and one mov. The other move/zeroing the
upper part of the register needs to be seperate as it is due to the intrinsic
being defined as an inline-assembly .
Referenced Bugs:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92665
[Bug 92665] [AArch64] low lanes select not optimized out for vmlal intrinsics
