https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94343
--- Comment #14 from Jakub Jelinek <jakub at gcc dot gnu.org> --- (In reply to jbeulich from comment #13) > As to using 512-bit operations even on more narrow input types - is this > correct when e.g. subsequently source code upcasts the vector? I.e. would > such an upcast be carried out by emitting an insn to zero the upper portion, > rather than simply considering this a re-interpretation of the same register > (with no insn emitted at all)? In which case the fix would apparently boil > down to using a mode iterator different from VI (VI48_AVX512VL if you really > mean to exclude vectors of QI/HI, or a combination of this and VI12_AVX512VL > otherwise). Yes, in RTL a store to a register in some machine mode when the hw register has wider mode leaves the upper bits undefined, not zero initialized (like e.g. most of the 32-bit instructions do on 64-bit general purpose registers or many AVX etc. instructions do on vector registers), we do have a REE pass to handle some most common cases. If we added some machine specific pass that would do something like that for most instructions, we'd need some attribute to mark instructions that don't have that property, sure, but we don't ATM.
