https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94052
--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The releases/gcc-8 branch has been updated by Tamar Christina <tnfch...@gcc.gnu.org>: https://gcc.gnu.org/g:0349bc70454e4de18d1cdf5eea0917646fdf79ae commit r8-10139-g0349bc70454e4de18d1cdf5eea0917646fdf79ae Author: Tamar Christina <tamar.christ...@arm.com> Date: Tue Mar 24 15:00:44 2020 +0000 AArch64: Break apart paradoxical subregs for VSTRUCT writes (PR target/94052) This works around an ICE in reload where from expand we get the following RTL generated for VSTRUCT mode writes: (insn 446 354 445 2 (set (reg:CI 383) (subreg:CI (reg:V4SI 291) 0)) "small.i":146:22 3408 {*aarch64_movci} (nil)) This sequence is trying to say two things: 1) liveliness: It's trying to say that eventually the whole CI reg will be written to. It does this by generating the paradoxical subreg. 2) write data: It's trying to in the same instruction also write the V4SI mode component at offset 0 in the CI reg. This patch fixes it by in the backend when we see such a paradoxical construction breaking it apart and issuing a clobber to correct the liveliness information and then emitting a normal subreg write for the component that the paradoxical subreg was trying to write to. Concretely we generate this: (insn 42 41 43 (clobber (reg/v:CI 122 [ diD.5226 ])) "small.i":121:23 -1 (nil)) (insn 43 42 44 (set (subreg:V4SI (reg/v:CI 122 [ diD.5226 ]) 0) (reg:V4SI 136)) "small.i":121:23 -1 (nil)) gcc/ChangeLog: PR target/94052 * config/aarch64/aarch64-simd.md (mov<mode>): Remove paradoxical subregs of VSTRUCT modes. gcc/testsuite/ChangeLog: * g++.target/aarch64/aarch64.exp: New file. * g++.target/aarch64/pr94052.C: New test.
