https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94037
--- Comment #7 from Richard Biener <rguenth at gcc dot gnu.org> --- (In reply to Uroš Bizjak from comment #5) > (In reply to Richard Biener from comment #4) > > (In reply to Uroš Bizjak from comment #3) > > > (In reply to Jakub Jelinek from comment #2) > > > > The > > > > setge %sil > > > > movzbl %sil, %esi > > > > to > > > > xorl %esi, %esi > > > > setge %sil > > > > > > This is quite important conversion, as the later avoids partial register > > > stall. > > > > Couldn't we fix this by pretending setge and friends produce SImode > > and always emit xor + setCC? So not rely on a peephole but emit > > the xor already during RTL expansion, eventually eliding it later > > if that's ever necessary. > > xor clobbers flags, so they would be killed before setCC. OTOH, "mov $0, > %reg" doesn't clobber flags, but it also doesn't break partial reg > dependency. Oh, ok. That means if we want to more aggressively persue this we need sth before RA. I guess splitting it before RA would then depend on some scheduling moving the zeroing somewhere before the CC computation... Or we even pull in the actual CC computation into the early non-split pattern.
