https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93893
Bug ID: 93893
Summary: MIPS32r2: GCC is unable to figure out that it can use
a single INS instruction instead of SLL+OR
Product: gcc
Version: 9.2.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: c
Assignee: unassigned at gcc dot gnu.org
Reporter: siarhei.siamashka at gmail dot com
Target Milestone: ---
Created attachment 47891
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=47891&action=edit
Testcase for a single INS instruction vs. SLL+OR
$ mipsel-unknown-linux-gnu-gcc -c -Os -march=mips32r2 testcase.c
$ mipsel-unknown-linux-gnu-objdump -d testcase.o
testcase.o: file format elf32-tradlittlemips
Disassembly of section .text:
00000000 <transpose_c>:
0: 8c820000 lw v0,0(a0)
4: 94a30000 lhu v1,0(a1)
8: 00021400 sll v0,v0,0x10
c: 00431025 or v0,v0,v1
10: 03e00008 jr ra
14: acc20000 sw v0,0(a2)
00000018 <transpose_inline_asm>:
18: 8ca20000 lw v0,0(a1)
1c: 8c830000 lw v1,0(a0)
20: 7c62fc04 ins v0,v1,0x10,0x10
24: 03e00008 jr ra
28: acc20000 sw v0,0(a2)
2c: 00000000 nop
The C implementation uses an extra instruction compared to the inline assembly
variant of the same function.
