https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93670
--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> --- Created attachment 47817 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=47817&action=edit gcc10-pr93670.patch VL vs. DQ vs. BW where only one or two but not all 3 are enabled is a mess :(. The extraction insns 32x4 256->128 are VL+F, 32x4 512->128 are F, 64x2 256->128 VL+DQ, 64x2 512->128 DQ, 32x8 512->256 DQ, 64x4 512->256 F, when not counting the nonmasked i128 in AVX2 and f128 in AVX.
