https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93453
Segher Boessenkool <segher at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2020-01-28
Ever confirmed|0 |1
--- Comment #1 from Segher Boessenkool <segher at gcc dot gnu.org> ---
The first case is because the splitter does
emit_insn (gen_ashldi3 (op3, op3, GEN_INT (32)));
emit_insn (gen_iordi3 (dest, dest, op3));
but this splitter runs late, so it has to do all wanted simple optimisations
manually.
The second is
Trying 7 -> 8:
7: r124:DI=r125:DI<<0x20
REG_DEAD r125:DI
8: r123:DI=r124:DI|r126:DI
REG_DEAD r126:DI
REG_DEAD r124:DI
Failed to match this instruction:
(set (reg:DI 123)
(ior:DI (ashift:DI (reg:DI 125)
(const_int 32 [0x20]))
(reg:DI 126)))
We need a separate pattern to also recognise this (instead of just a version
with the AND) if we already know the high half bits (of r126 here) are zero.
Confirmed.
