[Bug target/93333] ICE: RTL check: expected code 'const_int', have 'and' in riscv_rtx_costs, at config/riscv/riscv.c:1645

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93333

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org,
                   |                            |wilson at gcc dot gnu.org

--- Comment #1 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Can't reproduce with very similarly configured cross.
I do see:
Trying 14 -> 15:
   14: r86:SI=r90:SI 0>>r89:SI#0
      REG_DEAD r90:SI
      REG_DEAD r89:SI
   15: r87:SI=r86:SI&0x1f
      REG_DEAD r86:SI
Failed to match this instruction:
(set (reg:SI 87)
    (zero_extract:SI (reg:SI 90)
        (const_int 5 [0x5])
        (zero_extend:SI (subreg:QI (reg:SI 89) 0))))
Failed to match this instruction:
(set (reg:SI 87)
    (zero_extract:SI (reg:SI 90)
        (const_int 5 [0x5])
        (and:SI (reg:SI 89)
            (const_int 255 [0xff]))))
and
Failed to match this instruction:
(set (reg:SI 88 [ i ])
    (lshiftrt:SI (reg/v:SI 84 [ i ])
        (subreg:QI (zero_extract:SI (reg:SI 90)
                (const_int 5 [0x5])
                (zero_extend:SI (subreg:QI (reg:SI 89) 0))) 0)))
Failed to match this instruction:
(set (reg:SI 88 [ i ])
    (lshiftrt:SI (reg/v:SI 84 [ i ])
        (subreg:QI (zero_extract:SI (reg:SI 90)
                (const_int 5 [0x5])
                (and:SI (reg:SI 89)
                    (const_int 255 [0xff]))) 0)))
etc. in the combine dump, but no such zero_extract was ever matched (I couldn't
see how it could be, all the zero_extract riscv patterns require CONST_INT in
the last two operands) and I see no ZERO_EXTRACT in all the set_src_cost calls
called from make_extraction.

So, any special tuning/whatever that isn't shown?

The fix would likely be something along the lines of
--- gcc/config/riscv/riscv.c    2020-01-12 11:54:36.385413831 +0100
+++ gcc/config/riscv/riscv.c    2020-01-20 20:06:04.729542828 +0100
@@ -1642,7 +1642,10 @@ riscv_rtx_costs (rtx x, machine_mode mod

     case ZERO_EXTRACT:
       /* This is an SImode shift.  */
-      if (outer_code == SET && (INTVAL (XEXP (x, 2)) > 0)
-         && (INTVAL (XEXP (x, 1)) + INTVAL (XEXP (x, 2)) == 32))
+      if (outer_code == SET
+         && CONST_INT_P (XEXP (x, 1))
+         && CONST_INT_P (XEXP (x, 2))
+         && INTVAL (XEXP (x, 2)) > 0
+         && INTVAL (XEXP (x, 1)) + INTVAL (XEXP (x, 2)) == 32)
        {
          *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);

but I'd say being able to reproduce is important.