https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91913
Jakub Jelinek <jakub at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |jakub at gcc dot gnu.org
--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
The problem is that:
1) *arm_movsi_insn uses =rk <- rk constraints
2) *arm_cmpsi_insn uses r, r constraints
3) *movsi_compare0 uses =0,r <- r,r constraints
4) define_peephole2s support predicates and conditions, but don't support
constraints
We have
; This pattern is never tried by combine, so do it as a peephole
(define_peephole2
[(set (match_operand:SI 0 "arm_general_register_operand" "")
(match_operand:SI 1 "arm_general_register_operand" ""))
(set (reg:CC CC_REGNUM)
(compare:CC (match_dup 1) (const_int 0)))]
"TARGET_ARM"
[(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))
(set (match_dup 0) (match_dup 1))])]
""
)
Now, if we have (set sp r6) followed by (set cc (compare r6 (const_int 0)))
this peephole2 makes a *movsi_compare0 with sp destination and r6 input out of
it, but while that satisfies the s_register_operand predicate on
*movsi_compare0, it doesn't satisfy the "=r" constraint. I can't find a
predicate in arm.md that would accurately match the r constraint only, so
either one should be added, or we could do something like:
--- gcc/config/arm/arm.md.jj 2019-09-27 17:48:19.898511815 +0200
+++ gcc/config/arm/arm.md 2019-09-28 13:18:56.930913514 +0200
@@ -10398,7 +10398,7 @@
(match_operand:SI 1 "arm_general_register_operand" ""))
(set (reg:CC CC_REGNUM)
(compare:CC (match_dup 1) (const_int 0)))]
- "TARGET_ARM"
+ "TARGET_ARM && REG_P (operands[0]) && REGNO (operands[0]) != SP_REGNUM"
[(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int
0)))
(set (match_dup 0) (match_dup 1))])]
""
which fixes the ICE.
