https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91102
--- Comment #3 from Segher Boessenkool <segher at gcc dot gnu.org> ---
Before combine there were also
(insn 8 7 9 3 (set (reg/v:DI 95 [ c ])
(reg:DI 92 [ b$h ])) "91102.c":18:15 47 {*movdi_aarch64}
(nil))
(insn 11 10 12 3 (set (reg:DI 100)
(subreg:DI (reg:SI 99) 0)) "91102.c":19:12 47 {*movdi_aarch64}
(expr_list:REG_DEAD (reg:SI 99)
(nil)))
making in total
insn_cost 4 for 8: r95:DI=r92:DI
insn_cost 4 for 11: r100:DI=r99:SI#0
REG_DEAD r99:SI
insn_cost 4 for 12: zero_extract(r95:DI,0x20,0x20)=r100:DI
REG_DEAD r100:DI
insn_cost 4 for 15: x2:DI=r95:DI
REG_DEAD r95:DI
becoming
replacement cost 12
modifying insn i3 15: x2:DI=r92:DI&0xffffffff|r99:SI#0<<0x20
REG_DEAD r92:DI
REG_DEAD r99:SI
which is just fine afaics.
Or do we want to not have hard regs on outputs either? Do we get better
register allocation that way, for example?
