https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87763
--- Comment #54 from Wilco <wilco at gcc dot gnu.org> --- (In reply to Jeffrey A. Law from comment #53) > Realistically the register allocation issues are not going to get addressed > this cycle nor are improvements to the overall handling of RMW insns in > combine. So we're going to be stuck with bandaids. > > I've got an updated backend pattern that should address the remainder of the > insv_1 and insv_2 regressions and Steve has a backend pattern to address the > other regression in this BZ. I'd prefer not to add quick hacks that aren't beneficial in the long term. Adding a very general pattern to handle any bitfield insert of any constant would be much more useful. There is no issue with xfailing these tests - neither insv pattern was used frequently so the regression for these is not significant compared to the register allocation and move issues.
