https://gcc.gnu.org/bugzilla/show_bug.cgi?id=83377
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |NEW
Last reconfirmed| |2018-12-12
Ever confirmed|0 |1
--- Comment #6 from Richard Biener <rguenth at gcc dot gnu.org> ---
CCP does not have conditional information here (given it is based on SSA
propagation and doesn't insert ASSERT_EXPRs). The bit-tracking infrastructure
would need to be added for example to EVRP where conditional information
can be tracked. Still even SSA only has nonzero-bits and not the full
lattice the CCP machinery computes.
Note since the transform is to combine the and with AGU doing this on RTL
looks more appropriate (even if similarly difficult).
0: 40 f6 c7 02 test $0x2,%dil
4: 74 07 je d <b+0xd>
6: 48 83 e7 fd and $0xfffffffffffffffd,%rdi
a 3-insn peephole could do the trick? Or doesn't that work with control-flow?
I fear we have no RTL pass doing sth like VRP or bit tracking conditionally
(so even nonzero bits wouldn't work here, no?)
