https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87507
--- Comment #4 from Peter Bergner <bergner at gcc dot gnu.org> ---
So this seems to be coming from ira-costs.c:ira_tune_allocno_costs()
/* Some targets allow pseudos to be allocated to unaligned sequences
of hard registers. However, selecting an unaligned sequence can
unnecessarily restrict later allocations. So increase the cost of
unaligned hard regs to encourage the use of aligned hard regs. */
{
const int nregs = ira_reg_class_max_nregs[aclass][ALLOCNO_MODE (a)];
if (nregs > 1)
{
ira_allocate_and_set_costs
(&ALLOCNO_HARD_REG_COSTS (a), aclass, ALLOCNO_CLASS_COST (a));
reg_costs = ALLOCNO_HARD_REG_COSTS (a);
for (j = n - 1; j >= 0; j--)
{
regno = ira_non_ordered_class_hard_regs[aclass][j];
if ((regno % nregs) != 0)
{
int index = ira_class_hard_reg_index[aclass][regno];
ira_assert (index != -1);
reg_costs[index] += ALLOCNO_FREQ (a);
}
}
}
}
...which pessimizes odd/even register pairs (like r7,r8) over even/odd register
pairs (like r30,r31), but I think odd/even volatile pairs should still be
cheaper than even/odd non-volatile pairs. So maybe something like:
COST(even/odd volatile) < COST(odd/even volatile) < COST(even/odd
non-volatile) < COST(odd/even non-volatile)
??
