https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87433
Bug ID: 87433
Summary: gcc.dg/zero_bits_compound-1.c and
gcc.target/aarch64/ashltidisi.c regressions on aarch64
Product: gcc
Version: unknown
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: middle-end
Assignee: unassigned at gcc dot gnu.org
Reporter: sje at gcc dot gnu.org
Target Milestone: ---
The tests gcc.dg/zero_bits_compound-1.c and gcc.target/aarch64/ashltidisi.c
have been failing since this checkin:
commit 9fa26361aee8ed622921a36dd26d0b0ed0c75641
Author: segher <segher@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Mon Jul 30 13:18:17 2018 +0000
combine: Allow combining two insns to two insns
This patch allows combine to combine two insns into two. This helps
in many cases, by reducing instruction path length, and also allowing
further combinations to happen. PR85160 is a typical example of code
that it can improve.
This patch does not allow such combinations if either of the original
instructions was a simple move instruction. In those cases combining
the two instructions increases register pressure without improving the
code. With this move test register pressure does no longer increase
noticably as far as I can tell.
(At first I also didn't allow either of the resulting insns to be a
move instruction. But that is actually a very good thing to have, as
should have been obvious).
PR rtl-optimization/85160
* combine.c (is_just_move): New function.
(try_combine): Allow combining two instructions into two if neither of
the original instructions was a move.
